As an increasingly higher extent of integration is achieved in semiconductor integrated circuits in recent years, semiconductor devices need to adopt a multilayer wiring structure allowing wirings to be stacked over many layers. A semiconductor device adopting a multilayer wiring structure needs to include trench wiring that connects various elements laid out along the horizontal direction and via-hole wiring that connects various elements layered along the vertical direction. A low-resistance metal with an outstanding anti-electromigration property, such as copper, is often used as the wiring material and a highly porous low-k material that assures a low dielectric constant, is often used as the interlayer insulating material so as to achieve higher speed in the integrated circuit.
A wiring structure constituted with a low-dielectric constant insulating film (hereafter may be referred to as a “low-k film”) and a copper wiring such as that described above, may be formed as described below through, for instance, the damascene method. First, an insulating film is formed on a semiconductor wafer (hereafter may be referred to as a “wafer”) which is the processing target substrate and a wiring layer is formed by burying a copper wiring in the insulating film. Next, an etching stopper film, an interlayer insulating film constituted of a low-k material, a capping film and an anti-reflection coating are formed in this order over the wiring layer. Then, a photoresist film with a specific pattern corresponding to the wiring pattern is formed over the anti-reflection coating by using a photolithography technology. The photoresist film is used as a mask while etching through the anti-reflection coating, the capping film, the low-k film and the etching stopper film. As a result, a groove (trench) or a hole (via) to be used as a wiring recess is formed at the low-k film, with the surface of the copper wiring exposed at the bottom of the wiring groove or the wiring hole.
Next, the wafer undergoes an ashing process to remove the photoresist film and the anti-reflection coating. Subsequently, a wiring metal, e.g., copper, is embedded in the wiring groove or the wiring hole formed at the low-k film, and finally, any excess metal is removed through chemical-mechanical polishing (CMP). Part of the multilayer wiring structure is completed by thus connecting the horizontal copper wiring (wiring layer) with the vertical copper wiring.
The low-k film, which has become an indispensable element in a multilayer wiring structure as described above, tends to be readily damaged during the etching process or the ashing process. An area of the low-k film subjected to such damage readily absorbs water and, as a result, the dielectric constant over the area increases, resulting in an increase in the parasitic capacity between the wirings, which, in turn, may lead to a signal delay and compromise the electrical characteristics such as the insulation resistance. For this reason, a restoration process for restoring the film quality by repairing the damaged area of the low-k film or by rendering the low-k film hydrophobic is executed on the wafer having undergone the ashing process in the related art (see, for instance, patent reference literatures 1 and 2 listed below.
Today, a substrate processing apparatus equipped with a processing chamber where wafers undergo a specific type of processing must assure higher throughput, miniaturization, efficient space utilization and the like by continuously executing a plurality of types of processing within a single processing chamber. This requirement is addressed in substrate processing apparatuses that execute the ashing process and the restoration process as described above and substrate processing apparatuses capable of executing the ashing process and the restoration process within a single processing chamber have been proposed. For instance, patent reference literature 1 discloses a technology whereby after a wafer undergoes the etching process in a processing chamber, the wafer is ashed with oxygen radicals with the wafer temperature sustained at approximately 100° C.˜150° C. and then a restoration process is executed on the ashed wafer by using a gas (hereafter referred to as a “silylating gas”) containing a silylating agent such as TMSDMA (dimethylaminotrimethyl silane) or DMSDMA (dimethylsilyldimethylamine) without transferring the wafer into another processing chamber.
It is also known that when the ashing process is executed with oxygen radicals, the low-k film may become damaged to result in a very significant increase in its dielectric constant. Accordingly, the use of hydrogen radicals instead of oxygen radicals in the ashing process has been proposed in recent years (see patent reference literatures 3 through 5 listed below). An ashing process is normally executed with hydrogen radicals by setting the wafer temperature to a higher level (e.g., 250° C.˜400° C.) compared to the wafer temperature set for an ashing process executed with oxygen radicals. While the amount of damage to the low-k film is reduced through the use of hydrogen radicals, damage still occurs during the etching process. For this reason, it is desirable to execute a restoration process after the ashing process executed with hydrogen radicals.
However, the silylating gas used in the restoration processing in the related art tends to ignite at a relatively low temperature. For instance, the ignition point (explosion limit temperature) of TMSDMA is approximately 220° C. This means that the silylating gas may ignite as the silylating gas to be use in the restoration process is delivered into the processing chamber if the temperature of the wafer having undergone the ashing process in the same processing chamber is high.
The ashing process with oxygen radicals is executed with the wafer temperature set to a lower level (e.g., 100° C.˜150° C.) than the ignition point of the silylating gas (220° C. in the case of TMSDMA, for instance). Thus, the silylating gas delivered into the same processing chamber following the ashing process so as to immediately execute the restoration process in the processing chamber, is not likely to ignite.
Hydrogen radical processing, which is executed on the wafer sustaining a higher temperature (e.g., 250° C.˜400° C.) than the wafer temperature set for the oxygen radical processing, is more problematic in that a silylating gas with a low ignition point (e.g., 220° C.) delivered into the same processing chamber for the restoration process following the hydrogen radical processing is highly likely to ignite.
In short, the restoration process in the related art, executed by using a silylating gas with a low ignition point, cannot be executed in the same processing chamber where the ashing process has been executed with hydrogen radicals. Since this requires allocation of separate processing chambers for the ashing process and the restoration process in, for instance, a cluster-type substrate processing apparatus equipped with a plurality of processing chambers, miniaturization of the substrate processing apparatus and effective utilization of space have been hindered. There is an added concern that if a failure occurs in either the ashing process chamber or the restoration process chamber, continuous wafer transfer will be disabled.    (Patent reference literature 1) Japanese Laid Open Patent Publication No. 2006-049798    (Patent reference literature 2) Japanese Laid Open Patent Publication No. 2006-111740    (Patent reference literature 3) Japanese Laid Open Patent Publication No. 2006-073722    (Patent reference literature 4) Japanese Laid Open Patent Publication No. 2007-128981    (Patent reference literature 5) Japanese Laid Open Patent Publication No. 2007-502543